1. Technical Field
The present invention relates to memory region mapping optimization for input/output (I/O) adaptors. More specifically, it relates to a method and system for allocating shared address translation tables for memory regions of multiple I/O adaptors.
2. Background Information
Efficient I/O technologies are in great demand to provide high-speed data transfers and ultra low latencies for highly reliable and scalable computing and storage. Examples of such technologies include InfiniBand, an architecture and specification for data flow between processors and I/O devices that promises greater bandwidth and high expandability, and the Host Ethernet Adapter (HEA) which is a virtualized Ethernet adapter integrated directly into the high-speed I/O bus and offers high throughput and low latency for Ethernet connections. These I/O technologies utilize memory regions for the buffers that are used for the send and receive queues. The buffers are used for moving data, e.g. in Direct Memory Access (DMA). The memory regions vary in size, from as small as 4 kilobytes (KB) to as large as 2 terabytes (TB). Such memory regions are comprised of Address Translation Tables, which are used to determine the real address that is to be used as the source or target for a DMA operation when performing local or remote accesses with virtual addresses.